With the increasing importance of reducing the power consumption of computing platforms, the processor architecture and design trends are moving towards a direction where more opportunities of total power gating are being pursued.
Power gating is the technique wherein circuit blocks that are not in use are temporarily turned off to reduce the overall leakage power of the chip. This temporary shutdown time can also call as “low power mode” or “inactive mode”. In contrast, when circuit blocks are required for operation once again they are activated to “active mode”. These two modes are switched at the appropriate time and in the suitable manner to maximize power performance while minimizing impact to performance. Thus goal of power gating is to minimize leakage power by temporarily cutting power off to selective blocks that are not required in that mode.
As an electronic device transitions to a low power state from an active mode power state, the state information of the respective device is saved to ensure proper operation upon a subsequent exit from the low power state. Unfortunately, maintaining an excessive amount of on-die memory to store the necessary state information is cost prohibitive.
Typically, high speed interfaces utilize a physical layer and a link layer to facilitate the transmission of information. One example of a solution for an efficient means of exiting a low power state is a link reset for the layers associated with the high speed interface. The main purpose of the link reset is to recover a failing link. Nonetheless, this feature enables a control layer of an input/output interface that support multiples layers, such as, protocol, link, and physical to start operation with a clean slate immediately followed by a handshake and parameter exchange. However, in some cases, link reset is a destructive event for link layer control logic because any packets and information in flight will get dropped.